Current trends in the semiconductor and electronics industry require memory devices to be made smaller, faster and require less power consumption. One reason for these trends is that more personal devices are being manufactured that are relatively small and portable, thereby relying on battery power. In addition to being smaller and more portable, personal devices are also requiring increased memory and more computational power and speed. In light of all these trends, there is an ever increasing demand in the industry for smaller, faster, and lower power dissipation memory cells and transistors used to provide the core functionality of these memory devices.
Semiconductor memories can, for example, be characterized as volatile random access memories (RAMs) or nonvolatile read only memories (ROMs), where RAMs can either be static (SRAM) or dynamic (DRAM) differing mainly in the manner by which they store a state of a bit. An SRAM is typically arranged as a matrix of memory cells fabricated in an integrated circuit chip, and address decoding in the chip allows access to each cell for read/write functions. The basic CMOS SRAM cell generally includes two n-type or n-channel (nMOS) pull-down or drive transistors and two p-type (pMOS) pull-up or load transistors in a cross-coupled inverter configuration, with two additional NMOS select or pass-gate transistors added to make up a standard double-sided or differential six-transistor memory cell (a DS 6T SRAM cell, a 6T SRAM cell, or simply a 6T cell). 5 transistor SRAM cells (5T) and 4 transistor SRAM cells (4T) are also known. Additionally, application specific SRAM cells can include an even greater number of transistors, such as 8T and 9T cells. A plurality of transistors are utilized in SRAM requiring matched electrical characteristics to provide predictable cell switching characteristics, reliable circuit performance, and minimize array power dissipation.
FIG. 1 is schematic of a conventional differential SRAM 6T cell 100. As illustrated, the SRAM cell 100 comprises a data storage cell or latch 102, generally including a pair of cross-coupled inverters, for example, inverter 112, and inverter 114, the latch 102 operable to store a data bit state. FIG. 1 illustrates that the bit is stored in the latch 102 at the data nodes or first and second latch nodes 104 and 106, respectively, having a high or “1” state and a low or “0” state, respectively. Cell 100 also comprises a pair of wordline pass transistors 116, 118 to read and write the data bit between the cross-coupled inverters 112, 114 and bit lines BL 130, BL-bar 132, when enabled by wordline 134.
Respective inverters 112, 114 comprise a p-type MOS (PMOS) pull-up or load transistor Q1 120, Q2 122 and an n-type (nMOS) pull-down transistor Q3 124, Q4 126. Pass gates (e.g., transistors) Q5 116, Q6 118 are n-channel as well, which generally supply higher conductance as compared to p-channel transistors. Pass transistors 116, 118 are enabled by wordline 134 and accessed by bit lines 130, 132 to set or reset the SRAM latch 100. FIG. 1 further illustrates that inverters 112, 114 of the SRAM memory cell 100 are connected together to a Vdd drain power supply line 140 and a Vss source power supply line 150. Both the Vdd drain power supply line 140 and a Vss source power supply line 150 generally provide fixed voltage levels, such as 1.2 Volts and 0 Volts, respectively.
During conventional read or write operations, bit lines 130 and 132 are initially precharged to a high or “1” state as illustrated. A read voltage is asserted to wordline WL 134 during a read or a write operation to activate (turn-on) pass transistors Q5 116 and Q6 118 into conduction, whereby latch 102 may be accessed by bit lines BL 130 and BL-bar 132, respectively. The wordline voltage when asserted is generally the same as Vdd.
With the prior data states as shown in FIG. 1, an exemplary high state “1” is on a first latch node 104 at the gate of Q4 126, and a low state “0” is on a second latch node 106 at the gate of Q3 124. With these data states, only Q4 126 on the “low side” conducts (is on) and via latch node 106, and pulls bit line-bar 132 lower, while Q3 124 on the “high side” does not conduct (is off) and thus, leaves bit line 130 high. Thus, given a finite amount of time, the cell will increasingly establish a greater differential voltage between the bit lines 130 and 132 which can be sensed by a suitable sensing structure.
In general, SRAM cells are more stable and have better data retention where the respective pMOS (120, 122) and nMOS (124, 126) transistors are balanced and matched within the two inverters (112, 114). However, as dimensions are reduced to scale down devices, it becomes increasingly difficult to achieve a balance in the relative strengths (e.g. drive current capability) of the pass gate, drive, and load transistors over the desired range of temperature, bias conditions, and process variations, as well as achieving matched transistor characteristics. As a result, SRAM cells formed as such can be adversely affected by varying operating characteristics and may be unstable and may not be able to retain the desired bit state, during either or both the read or write operations.
Moreover, as transistor scaling trends continue, it becomes increasingly difficult to design an SRAM cell that has both adequate SNM, adequate Vtrip, and also can endure read and write operations over the desired operating range of temperature, bias conditions, and process variations. As known in the art, Vtrip is essentially a measure of the ability of a cell to be written into, and there is an interdependency between SNM and Vtrip in SRAM cell design. For example, if the pass gate is too strong relative to the drive transistor, SNM is degraded. If the pass gate is too weak relative to the drive transistor, Vtrip is degraded. Also, if the load transistor is too weak relative to the drive transistor, SNM is degraded.
Therefore, whatever generally improves SNM, also degrades Vtrip, and vice versa. With technology scaling to the 45 nm node and beyond, it may no longer be possible to achieve a balance in the relative strengths of the pass gate, drive, and load transistors over the desired range of temperature and bias conditions as well as process variations. Thus, with the increasing random variation of transistor characteristics with scaling, it is increasingly difficult to design an SRAM cell. Such challenges lead to consideration of circuit assists to improve SNM, Vtrip, and the read current (Iread). Unfortunately, these parameters have conflicting requirements. For example, assists that improve SNM generally degrade Vtrip, while assists that generally improve Vtrip degrade (Iread). Accordingly, there is a need for an improved SRAM cell design that is compatible with technology scaling to the 45 nm node and beyond, which that largely overcomes the performance tradeoffs and provides good performance during all operating conditions for SNM, Vtrip and Iread.